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[VHDL-FPGA-VerilogPCR

Description: 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
Platform: | Size: 4096 | Author: yagebu | Hits:

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